Pulse width forming circuits for generating pulse signals with a variety of pulse widths are used in many applications such as in a semiconductor test system. An example of such a pulse width forming circuit is shown in FIGS. 4A and 4B. FIG. 4A is a circuit diagram showing a configuration of the pulse width forming circuit and FIG. 4B is a timing chart showing the operation of the circuit of FIG. 4A. The pulse width forming circuit of FIG. 4A includes a pulse width integration circuit 30 and a pulse width differential circuit 45 connected in series.
The pulse width integration circuit 30 is formed of a first delay element 11 and an OR gate 13 to enlarge the pulse width of an incoming pulse signal. The pulse width integration circuit 30 receives an input pulse Pa of FIG. 4B(1) and produces a pulse Pb of FIG. 4B(2). The pulse Pb is produced by delaying the input pulse Pa by a first delay time D1 by the first delay element 11. At the output of the OR gate 13, the pulse width integration circuit 30 generates a pulse Pc shown in FIG. 4B(3) whose pulse width is integrated with the pulse width Pwa of the input pulse Pa and the delay time of the first delay element 11. Thus, a pulse width Pwc of the pulse Pc is the sum of the pulse width Pwa of the input pulse Pa and the first delay time D1.
The pulse width differential circuit 45 is formed of a second delay element 12 and an AND gate 14 to produce an output pulse having a predetermined pulse width. The pulse width differential circuit 45 receives the integrated pulse Pc of FIG. 4B(3) from the pulse width integration circuit 30 and produces a pulse Pd of FIG. 4B(4). The pulse Pd is produced by delaying the pulse Pc by a second delay time D2 by the second delay element 12. The pulse width differential circuit 45 generates an output pulse Pe shown in FIG. 4B(5) which starts at the falling edge of the pulse Pc and ends at the falling edge of the pulse Pd. The pulse width Pwe of the output pulse Pe is equal to the second delay time D2.
An example of the first and second delay elements 11 and 12 is a semiconductor gate circuit such as a CMOS gate whose propagation delay time can be controlled by a voltage supplied thereto. Another example of the delay elements is a passive circuit components such as a strip line or other signal transmission cables whose signal propagation delay times may be used as delay elements.
The conventional example in the foregoing has several disadvantages when used in the pulse width forming circuit. For example, to produce a desired pulse width based on the input pulse Pa of a small band width, the first delay element needs to have a relatively large delay time. However, the first delay time D1 must always smaller than the pulse width Pwa of the input pulse Pa to effectively enlarge the pulse width to produce the pulse Pc of FIG. 4B(3). Thus, the pulse width of the input pulse Pa must be greater than the delay time D1, which limits the range of pulse width of the input pulse Pa.
Further, the first delay time D1 is added to the pulse width Pwa of the input pulse Pa to produce the pulse Pc, and the start timing of the output pulse Pe is determined by the end timing of the pulse Pc. Thus, the delay time D1 affects the start timing of the output pulse Pe as shown in FIGS. 4B(3) and (5). Since delay time errors in such a delay element increase with the increase of the delay time, using the delay element having a relatively large delay time increases timing errors in the output pulse Pe.
In contrast, when the first delay time D1 is too small, the intended pulse width Pwe for the output pulse Pe may not be produced by the pulse width differential circuit 45. Such a case will occur when the sum of the delay time D1 and the pulse width Pwa of the input pulse Pa is smaller than the intended pulse width Pwe of the output pulse Pe, i.e., the second delay time D2. Thus, it is not practicable to use first delay element of too small delay time.
Another problem in the conventional pulse width formatting circuit of FIG. 4 is that there arises fluctuations in the output pulse timings. For example, since the delay elements 11 and 12 in FIG. 4A are typically formed of semiconductor devices such as CMOS gates, signal propagation times in such devices vary with the changes in the surrounding temperature, supply voltages, or the production process. For example, a signal propagation delay time of a typical CMOS gate fluctuates by a temperature of 0.3%/.degree. C. and by a source voltage of 0.4%/10 mV.
In the conventional example shown in FIGS. 4A and 4B, the pulse Pb from the first delay element 11, i.e., the end timing of the pulse Pc determines the start timing of the output pulse Pe as noted above. Therefore, the start timing of the output pulse Pe will be fluctuated with the changes in the delay time D1 in the first delay element 11. The timing fluctuations of the output pulse Pe is inappropriate for the semiconductor test system in which timing pulses with high accuracy must be used to test semiconductor devices with high accuracy.